1. Field of the Invention
The present invention relates to a delay route searching technique for logical circuits including LSIs, and more particularly to a delay route searching technique capable of reducing the process time and the storage capacity needed for the processing of delay route searching.
2. Description of the Related Art
When designing a logical circuit such as an LSI, it is necessary to search for any delay route and find out whether or not there is a logical path failing to satisfy the design standard on delay time. In doing so, if it is tried to individually assess the delay time of every logical pass in the logical circuit, tracing of the same route is often duplicated, taking an unnecessarily long processing time.
In order to solve this problem, the following method has been proposed (for instance as disclosed in the Japanese Patent Laid-open No. Hei 6-119411). This method will be described below with reference to FIG. 9, wherein reference signs A and B denote starting points; X and Y, end points; and G1 through G4, components positioned between the starting points and the end points.
By this method, first regarding component G1, the worst delay time TA1 from starting point A is figured out, and so is the worst delay time TB1 from starting point B at the same time. In this context, the longest delay time is deemed to be the worst delay time. After that, as information on component G1, as illustrated in FIG. 10, the identifier of starting point A, the delay time TA1 and the identifier of the immediately preceding component (starting point A in this case) on the route where the worst delay time occurs are stored in coordination with one another, and at the same time the identifier of starting point B, the delay time TB1 and the identifier of the immediately preceding component (starting point B in this case) on the route where the worst delay time occurs are also stored in coordination with one another.
Next, component G4 is subjected to similar processing, and such information as listed in FIG. 11 is stored as information on component G4. TB4 denotes the worst delay time between starting point B and component G4.
Then, regarding component G2, the worst delay time TA2 from starting point A is calculated, and so is the worst delay time TB2 from starting point B at the same time. The abovementioned delay time TB2 is figured out by adding the delay time TB4 stored as information on component G4 and the delay time T42 between components G4 and G2. After that, such information as listed in FIG. 12 is stored as information concerning component G2.
Next, regarding component G3, the worst delay time TA3 from starting point A is figured out, and so is the worst delay time TB3 from starting point B at the same time. The worst delay time TA3 is figured out in the following manner. The already stored worst delay time TA1 (see FIG. 10) from starting point A to component G1 and the delay time T13 between components G1 and G3 are added (TA1+T13), and the already stored worst delay time TA2 (see FIG. 12) from starting point A to component G2 and the delay time T23 between components G2 and G3 are added (TA1+T23). After that, the two sums are compared, and the greater sum is supposed to be the worst delay time TA3 from starting point A. Now, if (TA1+T13) is found smaller than (TA2+T23) for instance, the worst delay time TA3 from starting point A to component G3 is (TA2+T23). The worst delay time TB3 from starting point B to component G3 (which in this case is supposed to be TB4+T42+T23) can be calculated n the same manner. After that, such information as listed in FIG. 13 is stored as information on component G3.
End points X and Y are also subjected to similar processing, and information on these end points X and Y, such as shown in FIGS. 14 and 15, respectively, is stored.
By comparing the delay times in the information on end points X and Y shown in FIGS. 14 and 15, respectively, with the pertinent design standard on delay time, it can be found out whether or not there is any logical path violating the delay standard. Further, by using the identifier of the immediately preceding component included in the information shown in FIGS. 10 through 15, the logical path having the worst delay time can be identified.
According to the prior art method described above, since no duplication occurs in the tracing of routes, the processing time can be shorter than in the case where the delay time on every logical path in the logical circuit is individually figured out.
However, the above-described method according to the prior art, which needs the storage of information on each component and each end point with respect to every starting point (the worst delay time from the starting point, and the immediately preceding component), entails the problem of requiring a large storage capacity. Moreover, since it is needed to calculate the worst delay time for each component and each end point with respect to every starting point, the processing time cannot be reduced substantially. Although the logical circuit illustrated in FIG. 9 has only two starting points, an actual logical circuit, such as an LSI, may have dozens of starting points, necessitating a much greater storage capacity and a much longer processing time.
Besides the technique described above, the prior art includes another proposed technique, by which pre-layout-design delay information and post-layout-design delay information, for example, are compared, arcs for which the delay time in the post-layout-design delay information is longer are detected, and delay analyses are conducted only of routes involving the detected arcs (e.g. the Japanese Patent Laid-open No. Hei 9-6836). This technique, however, involves the problem that it is applicable only where pre-layout-design delay information and post-layout-design delay information are available.